Page 22 - circuitos Digitales

| Diseño de circuitos digitales usando VHDL y tarjeta Nexys 3

Código 1-3. Decodificador 2 a 4
1. library IEEE;
2. use IEEE.STD_LOGIC_1164.ALL;
3. entity IC_deco is
4. Port (G0 : in STD_LOGIC;
5. G1: in STD_LOGIC;
6. Y0: out STD_LOGIC;
7. Y1: out STD_LOGIC;
8. Y2: out STD_LOGIC;
9. Y3: out STD_LOGIC);
10. end IC_deco;
11. architecture Behavioral of IC_deco is
12. component compnot is
13. Port (D: in STD_LOGIC;
14. F: out STD_LOGIC);
15. end component;
16. component compand is
17. Port (A0 : in STD_LOGIC;
18. A1: in STD_LOGIC;
19. B: out STD_LOGIC);
20. end component;
21. Signal sg0,sg1,sg2: STD_LOGIC;
22. begin
23. ----SALIDA F0---
24. u0: compnot port map(D=>G0,F=>sg0);
25. u1: compnot port map(D=>G1,F=>sg1);
26. u3: compand port map(A0=>sg0,A1=>sg1,B=>Y0);
27. ------SALIDA F1----
28. u4: compand port map(A0=>G0,A1=>sg1,B=>Y1);
29. -----SALIDA F2-----
30. u5: compand port map(A0=>SG0,A1=>G1,B=>Y2);
31. ----SALIDA F3---
32. U6: compand port map(A0=>G1,A1=>G0,B=>Y3);
33. end Behavioral;
Fuente: los autores

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